1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and, more particularly, to the formation of an interconnect structure having contact plugs for connecting to contact regions of circuit elements, such as drain/source regions of a transistor.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a huge number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines that provide the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
For establishing the connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided that connects to a respective contact region of a circuit element, such as a gate electrode and the drain/source regions of transistors, and to a respective metal line in the first metallization layer. The contact plugs and regions of the contact structure are formed in an interlayer dielectric material that encloses and passivates the circuit elements.
During the formation of the respective contact plugs and regions, corresponding contact openings are formed in an interlayer dielectric material and these contact openings are subsequently filled with an appropriate material, such as a barrier material and tungsten or any other appropriate material. The formation of the contact openings is based on a photolithography step, during which the respective contact openings have to be aligned to respective contact regions of the circuit elements under question, such as source and drain regions of a transistor element, wherein, during the corresponding alignment procedure, slight misalignments may occur such that the corresponding contact opening may connect to undesired areas, such as an interface between an isolation trench and the active region, thereby resulting in a high risk for forming unwanted leakage current paths. In order to more clearly demonstrate the problems involved in the formation of contact plugs for circuit elements, such as transistor elements, an illustrative example of a conventional process technique will now be described with reference to FIG. 1.
FIG. 1 schematically shows a cross-sectional view of a conventional semiconductor device 100 comprising a substrate 101, above which is formed a circuit element 120 and an interconnect structure 130. The circuit element 120 may comprise an active semiconductor region or well region 103, which may be formed in an appropriate semiconductor layer 102, such as a silicon layer, wherein the active region 103 may be bordered by an isolation trench 112, which may be filled with any appropriate insulating material, such as silicon dioxide. Moreover, the circuit element 120 may comprise doped regions 104 and 104e within the active region 103, which may represent drain and source regions, wherein a dopant concentration in the regions 104 and 104e forms a PN junction, in combination with a corresponding inverse dopant concentration within the remaining semiconductor region 103, which may also be referred to body region. As is well known, a PN junction as formed by the doped regions 104, 104e, in combination with the well region 103, may be essential for the functioning of transistor elements, as well as for other circuit elements, such as conductive lines, capacitors, resistors and the like, as a conductive connection between the well region 103 and the doped regions 104, 104e is established upon application of appropriate electrical fields, while, otherwise, current flow, at least in one direction, may be substantially suppressed except for minor leakage currents.
Moreover, the circuit element 120, when represented by an illustrative transistor element, may comprise a gate electrode 105 formed above the region 103 that may be separated therefrom by a gate insulation layer 106. Typically, sidewall spacers 107 may be formed on sidewalls of the gate electrode 105, depending on device and process requirements.
The interconnect structure 130 may be comprised of an interlayer dielectric material 109 that is formed above the substrate 101 so as to surround the circuit element 120, wherein a contact etch stop layer 108 may be formed between the circuit element 120 and the interlayer dielectric material 109. Furthermore, the interconnect structure 130 comprises a contact region or contact plug 110 that is filled with a highly conductive material, such as tungsten, possibly in combination with a barrier material (not shown), so as to provide a highly conductive electric connection to a contact region of the circuit element 120, such as the drain and source region 104 and the gate electrode 105, which may comprise highly conductive metal silicide regions 113.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1 may comprise the following processes. After the formation of the circuit element 120 on the basis of well-established process techniques involving advanced photolithography, sophisticated deposition and etch techniques, advanced implantation processes, anneal sequences and advanced metal silicide formation techniques, the contact etch stop layer 108 may be formed above the circuit element 120 including the isolation trench 112 by well-established plasma enhanced chemical vapor deposition (PECVD) techniques. Thereafter, the interlayer dielectric material 109 may be deposited on the basis of, for instance, TEOS, oxygen and ozone in accordance with well-established chemical vapor deposition (CVD) techniques, wherein, optionally, the resulting layer 109 may be planarized by chemical mechanical polishing (CMP).
Next, an advanced lithography process may be performed, during which a contact pattern is transferred from a photolithography mask into a corresponding resist layer formed above the interlayer dielectric material 109, wherein the pattern of the lithography mask has to be aligned to the substrate 101 to position the contact plug 110 at an appropriate area within the circuit element 120 to establish the required electrical connection in an appropriate manner. Typically, the alignment process is very critical and a certain amount of misalignment has to be tolerated due to unavoidable insufficiencies or inaccuracies during the lithography process. Consequently, during a subsequent anisotropic etch process for forming a respective contact opening in the interlayer dielectric material 109 and subsequently in the contact etch stop layer 108, the contact opening may “land” on undesired circuit areas, such as the isolation trench 112, wherein the associated etch process may lead to irregularities within the respective contact opening, which may finally result after the filling of the contact opening with a conductive material to form the contact plug 110, in respective metal protrusions or irregularities 111. Depending on the process specifics, these protrusions 111 may even extend, in many cases, into the well region 103, thereby providing a direct contact from the contact plug 110 to the well region 103 by bridging the respective PN junction defined by the drain and source region 104 and the well region 103. In other cases, the corresponding metal protrusions 111 may provide increased leakage current paths, thereby also negatively affecting the operation of the circuit element 120. Consequently, due to substantially non-avoidable insufficiencies of the corresponding photolithography process, reduced performance or even failure of the corresponding circuit element 120 may result after the formation of the respective interconnect structure 130. However, increasing the area of the circuit element 120 that is available for receiving the contact plug 110 may be a less desirable option due to a significant increased amount of chip area which would be necessary in this case.
Thus, in view of the situation described above, a need exists for a more efficient technique for the formation of an interconnect structure while avoiding or at least reducing the effects of one or more of the problems identified above.